1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to an array substrate for use in the liquid crystal display (LCD) device.
2. Discussion of the Related Art
Recently, light and thin liquid crystal display (LCD) devices with low power consumption are widely used in office automation equipment, video devices, and the like. Such LCDs typically use an optical anisotropy and spontaneous polarization of a liquid crystal (LC). The liquid crystal material has thin and long liquid crystal molecules, which cause a directional alignment of the liquid crystal molecules. Initially, an alignment direction of the liquid crystal molecules is controlled by applying an electric field to the liquid crystal molecules. With the alignment direction of the liquid crystal molecules properly adjusted, light is refracted along the alignment direction of the liquid crystal molecules to display image data. Of particular interest, because of its high resolution and superiority in displaying moving pictures, is an active matrix (AM) LCD in which a plurality of thin film transistors and pixel electrodes are arranged in matrix array.
FIG. 1 shows an exploded perspective view illustrating a conventional LCD device. The LCD device 1 includes an upper substrate 5 and a lower substrate 10 that are spaced apart and face each other, and a liquid crystal layer 11 interposed therebetween. The upper substrate 5 and the lower substrate 10 are called a color filter substrate and an array substrate, respectively. On the rear surface of the upper substrate 5, a black matrix 6 and a color filter layer 7, including a plurality of red (R), green (G) and blue (B) color filters, are formed. The black matrix 6 surrounds each color filter forming an array matrix. The upper substrate 5 also includes a common electrode 9 covering the color filter layer 7 and the black matrix 6. The common electrode 9 is preferably made of a transparent conductive material.
On the front surface of the lower substrate 10, thin film transistors (TFTs) acting as switching elements, are formed in the shape of an array matrix corresponding to the color filter layer 7. In addition, a plurality of gate and data lines 12 and 24 cross each other such that each TFT is positioned near each crossing of the gate and data lines 12 and 24. Each individual pair of gate and pair of data lines 12 and 24 defines a pixel region P. In the pixel region P, a pixel electrode 46 is disposed. The pixel electrode 46 is formed of a transparent conductive material, such as indium tin oxide, which has an excellent transmissivity.
The LCD device having the above-mentioned structure displays color images by applying signals through the TFTs to the pixel electrodes 46. The gate line 12 applies a first signal to a gate electrode of the TFT, and the data line 24 applies a second signal to a source electrode of the TFT. Therefore, the LCD device drives the liquid crystal molecules using their electro-optic characteristics.
The liquid crystal layer 11 is a dielectric anisotropic material having spontaneous polarization characteristics. Due to their dipole and spontaneous polarization when electric signals are applied to the electrode 46 and to the common electrode 9, the liquid crystal molecules of the liquid crystal layer 11 are rearranged in accordance with the electric field. As the liquid crystal molecules are rearranged, the optical property of the liquid crystal layer changes creating an electro-optic modulation effect.
FIG. 2 is an enlarged plan view illustrating a portion of an array substrate for the conventional LCD device of FIG. 1. The arrangement of the liquid crystal layer 11 is controlled by an array substrate 52 having the gate line 12 apply a scanning signal and the data line 24 apply an image signal. The thin film transistor (TFT) is connected to both the gate line 12 and the data line 24, and disposed near the crossing of the gate and data lines 12 and 24, with the pixel electrode 46 positioned in the pixel region P and connected to the TFT.
As mentioned above, the gate lines 12 are arranged in a transverse direction, and the data lines 24 are arranged perpendicular to the gate lines 12. A pair of gate lines 12 and a pair of data lines 24 define each pixel region P. Each of thin film transistors (TFTs) is arranged at a position where the gate line 12 and the data line 24 cross one another. The pixel electrode 46 is disposed on the pixel region P defined by the pair of gate lines 12 and the pair of data lines 24.
Each TFT includes a gate electrode 14 to receive the scanning signal from the gate line 12, a source electrode 26 to receive the image signal from the data line 24, and a drain electrode 28 to connect the image signal to the pixel electrode 46. Further, each TFT includes an active layer 20 between the source electrode 26 and the drain electrode 28, with the drain electrode 28 facing the source electrode across the active layer 20. The active layer 20 is made of, for example, amorphous silicon (a-Si:H) or polycrystalline silicon. The gate electrode 14 extends from the gate line 12 and the source electrode 26 extends from the data line 24. The drain electrode 28 is connected to the pixel electrode 46 through a contact hole.
The pixel electrode 46 extends over the gate line 12 defining a storage capacitor C with a portion of the pixel electrode 46. Furthermore, gate pads 16 are formed at the end of the gate lines 12, respectively. A gate pad electrode 48 is disposed on each gate pad 16 to receive the scanning signal from a drive IC (not shown) and then applys the scanning signal to the gate lines 12 throughout the gate pad 16. Data pads 30 are disposed at the end of the data lines 24, respectively. A data pad electrode 50 is located on each data pad 30, to receive the image signal from a drive IC (not shown) and then to apply the image signal to the data line 24 through the data pad 30.
When the scanning signal is applied to the gate electrode 14 connected to the gate line 12, the TFT is activated (i.e., ON-STATE). The image signal is applied to the pixel electrode 46 through the TFT and the resulting electric field rearranges the liquid crystal by polarizing action.
Alternatively, when the scanning signal is not applied to the gate electrode 14, the TFT is not activated (i.e., OFF-STATE) and the image signal is not applied to the pixel electrode 46. In the OFF-STATE, the electric charges stored in the pixel region P are discharged to the TFT and to the liquid crystal. To prevent this discharge phenomenon, a storage capacitor C is connected in parallel to the pixel electrode 46. The storage capacitor C supplements the discharged electric charges with the stored electric charges. The storage capacitor C includes a capacitor electrode 32 that acts as a first electrode of the storage capacitor. A portion of the gate line 12 acts as a second electrode of the storage capacitor. The capacitor electrode 32 has an island shape and is positioned over the gate line 12, and the pixel electrode 46 contacts the island-shaped capacitor electrode 32 through a contact hole 38. With the capacitor electrode 32 interposed between the gate line 12 and the pixel electrode 46, the thickness of a dielectric layer of the storage capacitor C is minimized. Due to the thin dielectric layer, the capacitance of the storage capacitor can be raised.
With reference to FIGS. 3A to 3E, 4A to 4E, and 5A to 5E, a fabrication process for the conventional array substrate is explained. FIGS. 3A to 3E are sequential cross-sectional views taken along line III—III of FIG. 2, and illustrate manufacturing the thin film transistor and the pixel region. FIGS. 4A to 4E are sequential cross-sectional views taken along line IV—IV of FIG. 2, and illustrate forming the gate pad. FIGS. 5A to 5E are sequential cross-sectional views taken along line V—V of FIG. 2, and illustrate forming the data pad.
The fabrication process begins, as shown in FIGS. 3A, 4A and 5A, with a first metal deposited and patterned upon a transparent substrate 10 to form the gate line 12, the gate electrode 14, and the gate pad 16. Conventionally, the first metal employed is aluminum (Al), tungsten (W), molybdenum (Mo) or chromium (Cr). The gate line 12 extends from and connects with the gate pad 16, with the gate electrode 14 protruding from the gate line 12 (in FIG. 2). As discussed above, the gate pad 16 supplies the scanning signal to the gate line 12.
As shown in FIGS. 3B, 4B and 5B, a gate insulation layer 18 is formed on the transparent substrate 10 covering the metal layer previously formed. The gate insulation layer 18 may be an inorganic substance, such as silicon nitride (SiNx) or silicon oxide (SiO2), or an organic substance, such as benzocyclobutene (BCB) or acryl-based resin. Next, amorphous silicon (a-Si:H) and impurity-doped amorphous silicon (n+/p+a-Si:H) are formed in series on the gate insulation layer 18. The amorphous silicon and impurity-doped amorphous silicon are simultaneously patterned to form an active layer 20 and an ohmic contact layer 22, respectively. The active layer 20 is formed on the gate insulation layer 18, particularly over the gate electrode 14, and the ohmic contact layer 22 is formed over the active layer 20.
Next, as shown in FIGS. 3C, 4C and 5C, the source electrode 26 and the drain electrode 28 are formed from a second metal over the ohmic contact layer 22. By depositing and patterning the second metal, both the source electrode 26 and the drain electrode 28 are formed. Along with the data line 24 (in FIG. 2), the capacitor electrode 32 and the data pad 30 are formed on the gate insulation layer 18 such that the source electrode 26 extends from the data line 24. The source electrode 26 and the drain electrode 28 are spaced apart from each other and respectively overlap opposite ends of the gate electrode 14. The data pad 30 is positioned at the end of the data line 24 and supplies the image signal to the data line 24, as discussed above. The capacitor electrode 32 has an island shape and overlaps a portion of the gate line 12 to define the storage capacitor C of FIG. 2. Moreover, a portion of the ohmic contact layer 22 between the source electrode 26 and drain electrode 28 is eliminated to form a channel region CH.
Next, as shown in FIGS. 3D, 4D and 5D, a passivation layer 34 is formed on and over the above-mentioned intermediates with an organic substance such as benzocyclobutene (BCB) or an acryl-based resin. By patterning the passivation layer 34, a drain contact hole 36 is formed that exposes a portion of the drain electrode 28. Next, a capacitor contact hole 38 and a data pad contact hole 42 are also formed. The capacitor contact hole 38 exposes a portion of the capacitor electrode 32, and the data pad contact hole 42 exposes a portion of the data pad 30. Furthermore, by patterning both the passivation layer 34 and the gate insulation layer 18, a gate pad contact hole 40 is formed that exposes a portion of the gate pad 16.
Next, as shown in FIGS. 3E, 4E and 5E, a transparent conductive material, such as indium zinc oxide (IZO) or indium tin oxide (ITO), is deposited upon the passivation layer 34 having the contact holes and subsequently patterned to form the pixel electrode 46, the gate pad electrode 48 and the data pad electrode 50. As shown in FIG. 3E, the pixel electrode 46 electrically contacts the drain electrode 28 and the capacitor electrode 32 through the drain contact hole 36 and through the capacitor contact hole 38, respectively. As shown in FIG. 4E, the gate pad electrode 48 electrically contacts the gate pad 16 through the gate pad contact hole 40. As shown in FIG. SE, the data pad electrode 50 electrically contacts the data pad 30 through the data pad contact hole 42.
In the array substrate fabricated by the process described above, the storage capacitor C includes the overlapping portion of the gate line 12 as a first electrode, the capacitor electrode 32 as a second electrode, and the gate insulation layer as a dielectric layer. The pixel electrode 46 is electrically connected with the capacitor electrode 32. Furthermore, since the gate insulation layer 18 is interposed between the gate line 12 and the capacitor electrode 32 in the above-mentioned storage capacitor C, the gate insulation layer 18 acts only as a dielectric layer, that increases the capacitance of the storage capacitor C. The capacitor C does not use both the gate insulation layer and the passivation layer as a dielectric layer.
However, the processes described above have some drawbacks, especially during the process of forming the contact holes through the passivation layer 34. In FIG. 3E, the array substrate may be divided into the pixel region P where the pixel electrode 46 is disposed, a drain region D exists where the pixel electrode 46 contacts the drain electrode 28, and a storage region S exists where the storage capacitor C is disposed. In view of the drain region D, the layer structure consists of the gate insulation layer 18, the drain electrode 28 and the passivation layer 34. Alternatively, in the storage region S, the layer structure consists of the gate line 12, the gate insulation layer 18, the capacitor electrode 32 and the passivation layer 34. As compared with the drain region D, the storage region S includes one metal layer, i.e., the gate line 12. Additionally, the passivation layer 34 actually planarizes the surface of the array substrate. Therefore, the passivation layer 34 has different thickness in the drain region D and in the storage region S, respectively. A portion of the passivation layer 34 in the drain region D, directly over the drain electrode 28, is thicker than the respective storage region S, directly over the capacitor electrode 32. More specifically, the passivation layer 34 in the storage region S is as thin as a step of the gate line 12.
Accordingly, an over-etching occurs in the capacitor contact hole 38 when simultaneously forming the drain contact hole 36 and the capacitor contact hole 38 in the drain region D and in the storage region S using a dry etch method since the passivation layer 34 has different thicknesses at the drain region D and the storage region S.
Moreover, the over-etch of the capacitor contact hole 38 often exposes the lower gate line 12. Thus, although the pixel electrode 46 should be connected with only the capacitor electrode 32 when the pixel electrode 46 is formed on the passivation layer 34, the pixel electrode 46 comes in contact with the data line 12. When the pixel electrode 46 is connected to the gate line 12, the storage capacitor C does not operate properly. Specifically, since the capacitor electrode 32 (a first electrode of the storage capacitor) is short-circuited with the gate line 12 (a second electrode of the storage capacitor) by the pixel electrode 46, which results in the liquid crystal layer not being appropriately arranged, and causing the liquid crystal panel to malfunction.